1. Field of the Invention
The present invention relates to an output buffer and in particular to an output buffer for a semiconductor integrated circuit having a TTL interface.
2. Disclosure of the Prior
Referring now to FIG. 1, there is shown a circuit diagram showing a prior art output buffer.
In FIG. 1, an inductance L and a capacitance C which are connected with an output terminal O42 of an output buffer equivalently denote a signal transmission line having a characteristic impedance Z.sub.0 matched with that of the line. The output buffer complimentarily switches P and N channel MOS transistors P42 and N41 which are respectively connected between a first power source (hereinafter referred to as V.sub.DD) and the output terminal O42 via a drive circuit G41 comprising inverters 40 and 41 and between a second power source (hereinafter referred to as GND) and the output terminal O42 via a drive circuit G42 comprising inverters 42 and 43 in response to an input signal I41 for driving the load via the signal transmission line having the characteristic impedance Z.sub.0. In the output buffer for an integrated circuit having a TTL interface of a power source voltage which is 5 volts, the geometrical dimensions of P and N channel MOS transistors at the final stage and MOS transistors which form the drive circuits G41 and G42 are determined so that a delay time since the input signal I41 falls until the level on the output point O41 reaches 2 volts from the GND level and a delay times since the input signal I41 rises until the level on the output point reaches 0.8 volts from V.sub.DD meet the specifications.
Referring now to FIG. 2, there is shown a circuit diagram showing a prior art output buffer used for bidirectional input/output circuits such as data bus. The difference between the output buffers of FIGS. 1 and 2 resides in that the latter output buffer is capable of switching the P and N channel MOS transistors P51 and N51 between a drive state in which either one of the transistors is conductive and a high impedance state in which both transistors are non-conductive. The difference in circuit structure resides in that NOR gate 51 and NAND gate 53 are used in drive circuits G51 and G52, respectively and the state of the output point O52 is switched by these gates.
As mentioned above, it is necessary to change the voltage on the output point of the output buffer of the integrated circuit with a TTL interface having a power source of 5 voltages from 0.0 volt to 2.0 volts at rise time and from 5.0 volts to 0.8 volts at fall time, the change in the voltage of which is about double of that of the rise time.
Speed up of the output buffer has been demanded in accordance with the speed up of the system using integrated circuits. Accordingly, it is necessary to provide the same delay times at rise and fall times on the output point. Therefore, the output resistance of an N channel MOS transistor at the final stage of the output buffer should be a half of that of a P channel MOS transistor at the final stage. As shown at O41-1 and O51-1 in FIG. 3b, if the output resistance of the N channel MOS transistor at the final stage of the output buffer is the same as that of the P channel MOS transistor, that is, the characteristic impedance of the signal transmission line, no undershoot would occur while the delay time at rise time would be extended. As shown at O41-2 and O51-2 in FIG. 3b, if the output resistance of the N channel MOS transistor at the final stage of the output buffer is lower than a half of that of the P channel MOS transistor, that is, the characteristic impedance of the signal transmission line, an undershoot and a malfunction due to this undershoot would occur.